1. Technical Field
The present disclosure relates to a memory controller and, more particularly, to a dynamic memory refresh controller, a system including the same and a method of controlling refresh of dynamic memory.
2. Discussion of Related Art
Most system-on-chip (SOC) devices use some form of synchronous dynamic random-access memory (SDRAM), which has high density and low price, as a main memory. Basic data storage cells of the SDRAM, such as double data rate (DDR) or single data rate (SDR) SDRAM, have dynamic characteristics and, thus, a refresh operation for preserving data is required. Since this type of refresh operation typically consumes a lot of power, however, similar to that of a large-scale read operation, a refresh operation consuming a more suitable amount of power is required.
Dynamic memory is required to be refreshed periodically, and a cell may preserve data for tens to hundreds of milliseconds without being lost. One row of each page is refreshed by one refresh trigger and, thus, a practical period of a refresh trigger corresponds to just a few microseconds. Items related to a maximum refresh interval time (tREFImax), are included in all SDRAM specifications. When the refresh interval exceeds tREFImax, the preservation of data may not be guaranteed. Therefore, a memory controller needs to be designed so that the refresh interval does not exceed tREFImax. In addition, when the refresh operation collides with a normal access operation, such as a read or write operation, the refresh operation may not be performed. Therefore, the refresh operation must be performed within a shorter interval than tREFImax. This results in the dynamic memory being excessively refreshed, and the power consumption of a system including the dynamic memory is increased.
Many refresh controllers have difficulties in optimizing the refresh trigger interval. Assuming that data is accessed by transitioning a column after accessing a row address, when the maximum refresh interval is encountered, a precharge command is executed immediately, and the refresh trigger needs to be performed. When the refresh operation is completed, the corresponding row needs to be activated, and a following column address is accessed. Therefore, the dynamic memory may not be accessed at high speed, because more time for the precharging and the row activations is needed.
Many refresh controllers prevent a refresh trigger during accessing of the dynamic memory for responding to requests from a master device. Therefore, data may be lost when a read/write operation is performed at tREFImax.
FIG. 1 is a diagram useful in explaining a conventional method for preventing loss of data.
Referring to FIG. 1, most refresh controllers have a minimum time of tREFI that is set by users, and the dynamic memory is refreshed by providing a refresh trigger signal to the dynamic memory as soon as an idle state of the dynamic memory occurs after the set tREFI. A short tREFI is set for stably preserving data.
Therefore, the whole refresh interval becomes short, and the refresh trigger occurs more frequently during a fixed time interval. This results in the power consumption of the whole system being severely increased.